1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit embedded in a semiconductor integrated circuit requiring a high speed system clock to generate a plurality of single phase clock signals and multiphase clock signals with different frequencies.
2. Description of Related Art
FIG. 6 is a block diagram showing a conventional PLL circuit. In FIG. 6, the reference numeral 1 designates a phase comparator that compares the phase of a clock signal EC supplied to the PLL circuit (which will be referred to as an "external clock signal EC" from now on) with the phase of a frequency divided clock signal DC output from a frequency divider 6 (which will be referred to as a "frequency divided clock signal" below), and controls a pulse width of a pulse signal PA to be supplied to a charge pump 2 in accordance with the compared result; 2 designates the charge pump that adjusts the control voltage of a VCO (Voltage Controlled Oscillator) 4 in response to the width of the pulse signal supplied from the phase comparator 1; and 3 designates a low-pass filter (LPF) for eliminating harmonic noise contained in the control voltage of the VCO 4.
The reference numeral 4 designates the VCO for oscillating a clock signal CL with a frequency corresponding to the control voltage supplied from the charge pump 2 through the LPF 3 (which will be referred to as a "single phase clock signal" from now on); 5 designates a clock generator that generates a multiphase clock signal MCL from the single phase clock signal CL generated by the VCO 4, and outputs at least one of the single phase clock signal CL and multiphase clock signal MCL; and 6 designates the frequency divider that divides the frequency of the single phase clock signal CL oscillated by the VCO 4, and supplies the frequency divided clock signal DC to the phase comparator 1.
Next, the operation of the conventional PLL circuit will be described.
First, the phase comparator 1 of the PLL circuit compares the phase of the external clock signal EC with that of the frequency divided clock signal DC output from the frequency divider 6 to synchronize the single phase clock signal CL and the multiphase clock signal MCL with the external clock signal EC supplied to the PLL circuit.
If the phases of the two clock signals compared agree with each other, the phase comparator 1 suppresses the output of the pulse signal to be supplied to the charge pump 2, but if they disagree, the phase comparator 1 outputs the pulse signal with a width corresponding to the phase difference.
The pulse signal supplied to the charge pump 2 consists of two types of pulse signals, one for reducing the control voltage of the VCO 4, and the other for increasing it. More specifically, if the phase of the frequency divided clock signal DC lags behind the phase of the external clock signal EC, the pulse width of the pulse signal for increasing the control voltage of the VCO 4 is increased to advance the phase of the frequency divided clock signal DC. In contrast, if the phase of the frequency divided clock signal DC leads the phase of the external clock signal EC, the pulse width of the pulse signal for reducing the control voltage of the VCO 4 is increased to delay the phase of the frequency divided clock signal DC.
In response to one of the two types of the pulse signals supplied from the phase comparator 1, the charge pump 2 controls the control voltage of the VCO 4: the charge pump 2 increases the control voltage with the increase of the pulse width of the pulse signal for increasing the control voltage; and decreases the control voltage with the increase of the pulse width of the pulse signal for reducing the control voltage.
The LPF 3 removes the harmonic noise contained in the control voltage of the VCO 4 to reduce fluctuations in the control voltage by weakening the effect of the noise externally superimposed thereon, and supplies the VCO 4 with the control voltage with its noise removed.
Receiving the control voltage thus supplied from the LPF 3, the VCO 4 generates the single phase clock signal CL with the frequency corresponding to the control voltage. If the PLL circuit must generate a plurality of single phase clock signals and multiphase clock signals with different frequencies, the oscillation frequency of the VCO 4 must cover from a low to high frequency range. Thus, the oscillation frequency of the VCO 4 must be tuned over a wide range. FIG. 7 illustrates an example in which the oscillation frequency of the VCO 4 is tuned from 20 MHz to 100 MHz.
In response to the single phase clock signal CL generated by the VCO 4, the clock generator 5 generates the multiphase clock signal MCL, and outputs at least one of the single phase clock signal CL and multiphase clock signal MCL. When the PLL circuit must output the frequency divided clock signal DC of the single phase clock signal CL to the outside, the clock generator 5 includes a frequency divider for producing the frequency divided clock signal DC from the single phase clock signal CL to be supplied to the outside.
The frequency divider 6 supplies the phase comparator 1 with the frequency divided clock signal DC by dividing the frequency of the single phase clock signal CL generated by the VCO 4 to synchronize the single phase clock signal CL and multiphase clock signal MCL with the external clock signal EC.
Besides the foregoing prior art, Japanese patent application laid-open No. 2-234515/1990 discloses a technique that installs a plurality of VCOs in a PLL circuit. This technique, however, installs the plurality of VCOs to obtain an optimum loop noise band, but not to obtain a plurality of single phase clock signals or the like with different frequencies.
Although the conventional PLL circuit can output a plurality of single phase and multiphase clock signals with different frequencies with the foregoing configuration, it is not easy for the PLL circuit to tune the oscillation frequency of the VCO 4 over a wide range. In particular, the conventional PLL circuit has a problem in that it cannot increase the frequency of the single phase clock signal without deteriorating its frequency accuracy, because the tuning becomes increasingly difficult in a high frequency range.
Even if the oscillation frequency of the VCO 4 can be tuned over a wide range, the fluctuations in the oscillation frequency will become pronounced if the control voltage of the VCO 4 varies owing to noise or the like. Thus, a semiconductor integrated circuit using such a single phase clock signal as its system clock signal (a microcomputer embedded in a semiconductor integrated circuit, for example) is in danger of a malfunction.